allen-bradley slc 5 04 cpu manual

allen-bradley slc 5 04 cpu manual

Modular Processors. (Catalog Numbers 1747-L531, 1747-L532,. 1747-L541, 1747-L542, Manual. This value contains the.Guidelines Possessive form of james, Heaven's light our guide, Universitets guide, Lg vu cu920 user's manual, The gift of the magi teaching guide. Reload to refresh your session. Reload to refresh your session. Safety Guidelines for the Application, Installation and Maintenance of Solid State Controls (publication SGI-1.1 available from your local Rockwell Automation sales office or online at ) describes some important differences between solid state. Also, do not expose processor modules to surfaces or other areas that may typically hold an electrostatic charge. Electrostatic charges can alter or destroy memory. The SLC 500 modular processors must be inserted into the left slot (slot 0). POWER FORCE Indicates the LED indicator is ON. DH485 Indicates the LED indicator is FLASHING. BATT RS232 Status of LED indicator does not matter. Data in RAM is not lost if the battery is replaced within 30 minutes. Refer to the chapter on troubleshooting. In addition to the SLC 500 Modular Hardware Style User Manual, publication. Check your label to verify your processor’s current draw.Flash EPROMs (Flash Erasable Programmable Read Only Memory) combine the versatility of EEPROMs (Electrically-Erasable Programmable Read Only Memory) with the security of UVPROMs (UV-Erasable PROM). Transport by passenger aircraft is not permitted. Shipment of depleted batteries for disposal may be subject to specific regulation of. DH485 Indique que le voyant clignote.POWER FORCE Zeigt an, dass die LED-Anzeige AN ist. DH485 Zeigt an, dass die LED-Anzeige BLINKT. BATT RS232 Der Status der LED-Anzeige ist bedeutungslos. Den Stromverbrauch Ihres Prozessors finden Sie auf dem Etikett.Il manuale Safety Guidelines for the Application, Installation and Maintenance of Solid State Controls (pubblicazione SGI-1.http://www.euro-plast.biz.pl/galeria/file/fisher-ca-871-service-manual.xml

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1 disponibile presso l'Ufficio Commerciale Rockwell Automation di zona o online all'indirizzo ) descrive alcune differenze. I processori modulari SLC 500 devono essere inseriti nello slot di sinistra IMPORTANTE (slot 0). Fare riferimento al capitolo relativo alla ricerca guasti. Controllare l'etichetta per verificare l'assorbimento del processore.Tale clausola autorizza il trasporto di batterie al litio su veicoli a motore, treni merci, navi ed aerei da trasporto, previo soddisfacimento di determinate condizioni. Los procesadores modulares SLC 500 deben insertarse en la ranura izquierda IMPORTANTE (ranura 0). Consulte la etiqueta para verificar el consumo de corriente de su procesador.Os processadores modulares SLC 500 devem ser encaixados no slot da IMPORTANTE esquerda (slot 0). POWER FORCE LED indicador aceso. DH485 LED indicador piscando.Verifique na etiqueta o consumo de corrente de seu processador. You can view or download publications at To order paper copies of technical documentation, contact your local Rockwell Automation distributor or sales representative. Allen-Bradley Auto Publication 1747-IN009E-MU-P - April 2007. Trademarks not belonging to Rockwell Automation are the property of their respective companies. Automation has not reviewed or authorized this page, and DOES. NOT make any guarentees or warantees based on my extracts ofWhat I wantNOTHING of it's suitability for use in other applications.Automation documentation for the A-B product that you intend to useI am NOT qualified by Rockwell Automation,Unless specificallyManuals The PLC2 and. PLC3 are too ancient (pre-1985), getting the correct software is problematic. Despite the similarity in numbers they're actuallyUnless you already have pilesThe available memory options are 16K, 32K,Control.http://vendsol.com/userfiles/bush-portable-dvd-player-user-manual.xml

You can only changeYou cannot performWhen the keyswitch is left in the RUN position,The processorYou can only changeWhen the keyswitch is left in the PROG position,REMote Run, REMote Program, or REMote Test mode. You can change the processorYou can perform online program editingWhen the keyswitch is in the REM position, youDefaults Factory Defaults VBB and GND connections and hold for 60 seconds. This returns the processorMemory Module Data in RAM is not lostRequires uvprom programming equipment. PROM programmers to program and erase memory modules. The memory moduleAdapter Socket for 1747-M13 These modules include a high-speed counter module, a BASIC language module,Each provides a uniqueLoad) 16 inputs ?TTL input ?BCD inputs High-density for limited panelInput Module Input Module Input Module Inrush Amps The terminals on the 1746-P1 and -P2 provide an isolated, nonfused 200Was there ever a DOS version?) RSLogix 500 is compatible with. To browse Academia.edu and the wider internet faster and more securely, please take a few seconds to upgrade your browser. You can download the paper by clicking the button above. PDF Supply is not an authorized distributor, reseller or representative of the products featured on this website. The depiction, description or sale of products featuring these names, trademarks, brands and logos is for identification purposes only and is not intended to indicate any affiliation with or authorization by any rights holder. The 1747-L541 is compatible with the 1747-M13 memory module Series C OS401 or later, which supports up to 64K of user-memory backup.The backplane current at 5V is 1000mA and at 24V is 200 mA. In case of brief power loss, the 1747-L541 provides a program scan hold-up time of 20 ms - 3 seconds to prevent corruption of the system. Exact times depend on the power supply load. There are 30 chassis module slots in the CPU. Bit execution for the 1747-L541 is 0.37 microseconds.

The minimum thermal dissipation is 4 Watts for the unit. It has a 1 ms Selectable Time Interrupt (STI) and a 0.5 ms Discrete Input Interrupt (DII). The 1747-L541 also includes advanced math features such as trigonometry functions, PID, floating point, and compute instruction. The quantity you tried to add to your cart is unavailable. Go To Cart Close The products listed on this website may vary as to their country of origin; the accessories, and other items included with the product; and the language used on the packaging, the parts, and any related instructions or printed material related to the products. This website is not sanctioned or approved by any manufacturer or tradename listed. Designated trademarks, brand names and brands appearing herein are the property of their respective owners. Javascript and Cookies must be enabled to checkout.Our Website may contain our service marks or trademarks as well as those of our affiliates or other companies, in the form of words, graphics, and logos. Our Content, as found within our Website, Blogs and Services, is protected under United States and foreign copyrights. The copying, redistribution, use or publication by you of any such Content, is strictly prohibited. Your use of our Website and Services does not grant you any ownership rights to our Content. Older PLCs, however, tend to use a myriad of different cables and protocols. With a large number of legacy systems, the original programming cables and software are often long lost by the time you want to make updates or need to troubleshoot an issue. This blog post summarizes the different ways that you can connect to these PLCs and some of the pitfalls to look out for. The two most common ways to connect are DH-485 and DF1.The official A-B cable is 1747-CP3. In addition, you will need the female-to-female null modem crossover DB9 serial cable or a straight-through RJ45 ethernet cable, depending on which port you want to connect to.

Make sure you also set the selector switch to RS232 or RS 485. However, it is possible to configure it in the PLC settings to be 1200, 2400, or 9600 baud at as well. If you have an original A-B unit, it is possible to change to the baud rate to 9600 by following the steps in this Rockwell knowledgebase document (requires creating a free account and logging in). It comes installed as part of RSLogix 500, or you can download RSLinx Classic Lite for free from Rockwell. Select the right COM port and click Auto-Configure. The driver should be able to figure out the correct settings. Select the right COM port and click OK. Interacting with then successfully requires an intricate understanding of how they work. You must also possess the expertise to program them to work for you. There are many PLC courses designed for beginners. visit: Louis, MO 63117 (314) 627-5427. Please upgrade your browser to improve your experience. Please enable cookies in your browser to submit your RFQ online. You may also use our online contact us form or call us at shared-modal-phone-number Choose from our overstock inventory and save on 1747-L542. Santa Clara Systems carries 51,785 items from Allen Bradley. Santa Clara Systems, Inc. Because of \nthis difference, and also because of the wide variety of uses for solid state equipment, \nall persons responsible for applying this equipment must satisfy themselves that each \nintended application of this equipment is acceptable.\nIn no event will Rockwell Automation, Inc.If you do not, obtain the proper training before using this \nproduct.\n \n Purpose of This Manual This manual is a reference guide for SLC 500 controllers. Allen-Bradley Industrial Automation \nGlossary\n \n AG-7.1 \n\n Publication 1747-RM001F-EN-P - June 2008 \n\n \n \n Chapter 1\n \n Processor Files\n \n File Structure SLC 500 user memory is comprised of Data Files and Program Files.\n \n TIP The file types shown below for data files 3 through 8 \nare the default values.

Bits in \nfile 1 are used to represent external inputs. In most cases, a single 16-bit word \nin these files will correspond to a slot location in your controller, with bit \nnumbers corresponding to input or output terminal numbers. Unused bits of \nthe word are not available for use.\n \n Table 1.1 explains the addressing format for outputs and inputs. Note that the \nformat specifies e as the slot number and s as the word number. See Table 1.2 to understand \nhow to address various bits and words within the status file. You can address \nvarious bits and words as follows.\n \n Bit Data File (B3:)\n \n File 3 is the bit file, used primarily for bit (relay logic) instructions, shift \nregisters, and sequencers. The maximum size of the file is 256 1-word \nelements, a total of 4096 bits. You can address bits by specifying the element \nnumber (0 to 255) and the bit number (0 to 15) within the element. You can \nalso address bits by numbering them in sequence, 0 to 4095.\n \n You can also address elements of this file. See Table 1.3 for a detailed format \ndescription. The upper byte is the watchdog scan time. \n\n Publication 1747-RM001F-EN-P - June 2008 \n\n \n 1-4 Processor Files \n\n Timer Data File (T4:)\n \n Timer instructions use various control bits. These are 3-word elements, used \nwith Bit, TON, TOF and RTO instructions. Word 0 is the status word, word 1 \nindicates the preset value, and word 2 indicates accumulator value. Number 3 is the default file. A file number between 9-255 can be used if \nadditional storage is required.\n \n: Element delimiter\n \n e Element number Ranges from 0-255. If the skip \nduration is less than 2.5 seconds, no time will be lost; \nif the skip duration exceeds 2.5 seconds, an \nundetectable timing error occurs. Word 0 is the \ncontrol word, containing the status bits of the instruction. Word 1 is the preset \nvalue. The \nfollowing parameters detail the operations of the counter.

\n \n Accumulator Value (ACC)\n \n This is the number of false-to-true transitions that have occurred since the \ncounter was last reset.\n \n Preset Value (PRE)\n \n Specifies the value which the counter must reach before the controller sets the \ndone bit (DN). When the accumulator value becomes equal to or greater than \nthe preset value, the done status bit is set. These are 3-word elements, used \nwith bit shift, FIFO, LIFO, sequencer instructions, and ASCII instructions \nABL, ACB, AHL, ARD, ARL, AWA, and AWT. Word 0 is the status word, \nword 1 indicates the length of stored data, and word 2 indicates position. This \nis shown in Table 1.10.\n \n In the control element, there are eight status bits and an error code byte. Number 6 is the default file. A \nfile number between 9 and 255 can be used \nif additional storage is required.\n \n: Element delimiter\n \n e Element number Ranges from 0 to \n255. Number 7 is the default file. A \nfile number between 9 to255 can be used if \nadditional storage is required.\n \n: Element delimiter\n \n e Element number Ranges from 0 to \n255. These are 2-word elements, \naddressable at the element and bit level.\n \n Assign float addresses as follows.\n \n Table 1.14 Float File Addressing Format\n \n Format Explanation\n \n Ff:e\nF Integer file\n \n f File number. Number 8 is the default file. A \nfile number between 9 to 255 can be used if \nadditional storage is required.\n \n: Element delimiter\n \n e Element number Ranges from 0 to \n255. During operation, the processor \nmay set or reset the bit, based on logical continuity of ladder rungs. OTL can only turn on a bit, \nwhile OTU can only turn off a bit. Once the error conditions are cleared, the \ncontroller resumes operation using the data table \nvalue of the operand. \n\n Publication 1747-RM001F-EN-P - June 2008 \n\n \n Basic Instructions 2-5 \n\n When enabled, the latch instruction tells the controller to turn on the \naddressed bit.

Use the OSR instruction when an event must start based on \nthe change of state of the rung from false-to-true.\n \n When the rung conditions preceding the OSR instruction go from \nfalse-to-true, the OSR instruction will be true for one scan. After one scan is \ncomplete, the OSR instruction becomes false, even if the rung conditions \npreceding it remain true. This address allows the OSR instruction to remember its previous \nrung state.\n \n Use a bit address from either the bit or integer data file. The \noutput goes false and remains false for successive scans until the input makes \nanother false-to-true transition.\n \n In this case, the accumulated value of a timer is converted to BCD and moved to an \noutput word where an LED display is connected. When the timer is running, the \naccumulated value is changing rapidly. They also allow input conditions after the OSR \ninstruction. Input branching around an OSR instruction is not allowed.\n \n Timer Instructions \nOverview\n \n Entering Parameters\n \n These are several parameters associated with Timer instructions. The \nfollowing paragraphs detail the operation of the timer instruction.\n \n Accumulator Value (.ACC)\n \n This is the time elapsed since the timer was last reset. When enabled, the timer \nupdates this continually.\n \n Preset Value (.PRE)\n \n This specifies the value which the timer must reach before the controller sets \nthe done bit. When the accumulated value becomes equal to or greater than \nthe preset value, the done (DN) bit is set. The TON instruction begins to count timebase \nintervals when rung conditions become true. As long as rung conditions \nremain true, the timer adjusts its accumulated value (ACC) each evaluation \nuntil it reaches the preset value (PRE). The TOF instruction begins to count timebase \nintervals when the rung makes a true-to-false transition.

Rung \ntransitions can be caused by events occurring in the program (from internal \nlogic or by external field devices) such as parts traveling past a detector or \nactuating a limit switch.\n \n When rung conditions for a CTU instruction have made a false-to-true \ntransition, the accumulated value is incremented by one count, provided that \nthe rung containing the CTU instruction is evaluated between these \ntransitions. The ability of the counter to detect false-to-true transitions \ndepends on the speed (frequency) of the incoming signal.\n \n The accumulated value is retained when the rung conditions again become \nfalse. Also, the on \nor off status of counter done, overflow, and underflow bits is retentive. The \naccumulated value and control bits are reset when the appropriate RES \ninstruction is enabled. The CU bits are always set prior to entering the REM \nRun or REM Test modes.\n \n Count Down (CTD) The CTD is an instruction that counts false-to-true rung transitions. Rung \ntransitions can be caused by events occurring in the program such as parts \ntraveling past a detector or actuating a limit switch.\n \n When rung conditions for a CTD instruction have made a false-to-true \ntransition, the accumulated value is decremented by one count, provided that \nthe rung containing the CTD instruction is evaluated between these \ntransitions.\n \n The accumulated counts are retained when the rung conditions again become \nfalse. The \naccumulated value and control bits are reset when the appropriate RES \ninstruction is executed. The CD bits are always set prior to entering the REM \nRun or REM Test modes.\n \n High-speed Counter (HSC) The High-speed Counter is a variation of the CTU counter. One HSC instruction is allowed per controller. To use the \ninstruction, you must cut the jumper as shown below. This word is updated each \ntime the HSC instruction is evaluated and when the update accumulator \nbit is set using an OTE instruction.

This accumulator is read only. The CTU and CTD are \nsoftware counters. The HSC is a hardware counter and operates \nasynchronously to the ladder program scan. The HSC accumulated value \n(C5:0.ACC) is normally updated each time the HSC rung is evaluated in the \nladder program. This means that the HSC hardware accumulator value is \ntransferred to the HSC software accumulator. Only use the OTE instruction \nto transfer this value. These rungs poll the status of the HSC done bit. When the Done \nbit is set at any of these poll points, program execution moves to subroutine \nfile 3, executing the HSC logic. When the RES instruction is \nenabled, it resets the Timer On Delay (TON), Retentive Timer (RTO), Count \nUp (CTU), or Count Down (CTD) instruction having the same address as the \nRES instruction.\n \n When resetting a counter, if the RES instruction is enabled and the counter \nrung is enabled, the CU or CD bit is reset.\n \n If the counter preset value is negative, the RES instruction sets the \naccumulated value to zero. Otherwise, unpredictable \nmachine operation or injury to personnel may occur. \n\n Publication 1747-RM001F-EN-P - June 2008 \n\n \n \n Chapter 3\n \n Comparison Instructions\n \n This chapter contains general information about comparison instructions and \nexplains how they function in your application program. As an example, suppose a LES instruction is \npresented with two values. If source A and \nsource B are equal, the instruction is logically true. If these values are not \nequal, the instruction is logically false.\n \n Source A must be an address. Source B can either be a program constant or a \naddress. If source A \nand source B are not equal, the instruction is logically true. If the two values \nare equal, the instruction is logically false.\n \n Source A must be an address. Source B can be either a program constant or an \naddress. If source A is less than the value at source B, the \ninstruction is logically true.

If the value at source A is greater than or equal to \nthe value at source B, the instruction is logically false.\n \n Source A must be an address. Source B can either be a program constant or an \naddress. If the value at source A is less than or equal to the \nvalue at source B, the instruction is logically true. If the value at source A is \ngreater than the value at source B, the instruction is logically false.\n \n Source A must be an address. If the value at source A is greater than the value at source \nB, the instruction is logically true. If the value at source A is less than or equal \nto the value at source B, the instruction is logically false.\n \n Source A must be an address. If the value at source A is greater than or equal \nto the value at source B, the instruction is logically true. If the value at source \nA is less than the value at source B, the instruction is logically false.\n \n Source A must be an address. The instruction \nbecomes false as soon as it detects a mismatch. If the Test value is outside the limits, the instruction is false, as \nshown below.\n \n If the Low Limit has a value greater than the High Limit, the instruction is \nfalse when the Test value is between the limits. This can be word \naddresses or program constants. The rung must be between the overflow point and the END, TND, \nor REF statement.\n \n Updates to the Math Register, S:13 and S:14\n \n Status word S:13 contains the least significant word of the 32-bit value of the \nMUL instruction. It contains the remainder for DIV and DDV instructions. It \nalso contains the first four BCD digits for the Convert from BCD (FRD) and \nConvert to BCD (TOD) instructions.\n \n Status word S:14 contains the most significant word of the 32-bit value of the \nMUL instruction. It contains the unrounded quotient for DIV and DDV \ninstructions. These are 2-word elements and addressable only at the \nelement level.\n \n Assign floating point addresses as follows.\n \n Table 4.

3 Addressing Format\n \n Format Explanation\nFf:e F Floating Point file\n \n f File number. On \noverflow, the minor error flag is also set. For floating point, the \noverflow value is placed in the destination. For an integer, the \nvalue -32,768 or 32,767 is placed in the destination. On underflow, the minor error \nflag is also set. For floating point, the overflow value is placed in \nthe destination. For an integer, the value -32,768 or 32,767 is \nplaced in the destination. Use the Data Monitor function to make \nthis selection prior to entering the Run mode. \n\n Publication 1747-RM001F-EN-P - June 2008 \n\n \n Math Instructions 4-7 \n\n Example of 32-bit Addition\n \n The following example shows how a 16-bit signed integer is added to a 32-bit \nsigned integer. The decimal value of a 32-bit integer is derived from the displayed binary or hex value. This result is valid at overflow.\n \n Divide (DIV)\n Use the DIV instruction to divide one value (source A) by another (source B). \nThe rounded quotient is then placed in the destination. If the remainder is 0.5 \nor greater, round up occurs in the destination. The unrounded quotient is \nstored in the most significant word of the math register. The value -32,768 or \n32,767 is placed in the destination. The value 32,767 is \nplaced in the destination. If the remainder is 0.5 or \ngreater, the destination is rounded up.\n \n Updates to Arithmetic Status Bits\n \n The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. \nAfter an instruction is executed, the arithmetic status bits in the status file are \nupdated. \n \n Updates to the Math Registers, S:13 and S:14\n \n Initially contains the dividend of the DDV operation. Upon instruction \nexecution, the unrounded quotient is placed in the most significant word of \nthe math register. On overflow, the minor \nerror flag is also set. This instruction supports \ninteger and floating point values.

The input \nvalue can go outside of the specified input limits and \nno ordering is required. A pressure transducer is connected to input 0 and we \nwant to read the value in engineering units. The pressure transducer measures \npressures from 0 to 1000 psi and provides a 0 to 10V signal to the analog \nmodule. For a 0 to 10V signal, the analog module provides a range between 0 \nto 32,767. We want to control the proportional valve connected to \noutput 0. The valve takes a \n4 to 20 mA signal to control how far it opens (0 to 100%). (Assume that \nadditional logic is present in the program that calculates how far to open the \nvalve in percent and places a number between 0 and 100 into N7:21.) The \nanalog module provides a 4 to 20 mA output signal for a number between \n6242 to 31,208. The following program rung directs an analog output to \nprovide a 4 to 20 mA signal to the proportional valve (N7:21), based on a \nnumber between 0 and 100.\n \n Scale Data (SCL) When this instruction is true, the value at the source address is multiplied by \nthe rate value. The \nresult, 377, is placed in the destination. \n\n Publication 1747-RM001F-EN-P - June 2008 \n\n \n 4-16 Math Instructions \n\n Note that the term rate is sometimes referred to as slope. This must occur before the end of \nthe current scan to prevent major error code 0020 \nfrom being declared. The presence of an overflow is \nchecked before and after the offset value is applied.(1)\n \n (1) If the result of the Source times the Rate, divided by 10000, is greater than 32767, the SCL instruction \noverflows, causing error 0020 (Minor Error Bit), and places 32767 in the Destination. This \nhappens because the overflow condition occurred during the rate calculation. \n \n The following graph shows the shifted linear relationship. If the \nparameters are valid, the ramp function places the calculated output value in \nthe destination register.

The parameters are validated for every scan when the \nrung state is true. When the Ramp instruction is scanned and the rung state is \ntrue, the current time is updated, the destination value is calculated, and done \ncondition is checked.\n \n When the rung state is false, the current time is not updated and the \ndestination value is not calculated. When the rung state sees another false to \ntrue change the current time is determined from the last updated position. If a Ramp instruction is executing when a \npower cycle occurs, the instruction continues to operate starting with the last \nupdated position. The accuracy is limited to one unit or one scan, whichever is \nlarger. Ramp instructions can be cascaded.\n \n ATTENTION Changing words 1 through 4 during instruction \nexecution causes loss of resolution of one unit of \nmeasurement (1 second or 0.01 seconds depending \non ramp). This instruction supports integer and floating \npoint values. You define the operation in the Expression and the result is written \nin the Destination. The address is limited to integer constants. For bit, integer, and \nASCII file types, the length range is 1 to 128. For the string file type, the \nlength range is 1 to 41. The source must be greater than zero. If the value in source A is negative, the \nexponent (source B) should be a whole number. If it is not a whole number, \nthe overflow bit is set and the absolute value of the base is used in the \ncalculation. Searches the source from the \nlowest to the highest bit, and looks for the first set bit. The FFU unloads a word from the stack on \nsuccessive false- to-true transitions. The first word loaded is the first to be \nunloaded.\n \n 5-26\n \n LFL and LFU LIFO Load and\nLIFO Unload\n \n The LFL instruction loads a word into a LIFO stack on successive \nfalse-to-true transitions. The LFU unloads a word from the stack on \nsuccessive false-to-true transitions. This result is valid at \noverflow.

\n \n Example 1\n \n The integer value 9760 stored at N7:3 is converted to BCD and the BCD \nequivalent is stored in N10:0. The maximum BCD value possible is 9999.\n \n Example 2\n \n The integer value 32760 stored at N7:3 is converted to BCD. The 5-digit BCD \nvalue is stored in the math register. Status word S:14 is then cleared to make certain that unwanted data is \nnot present when the FRD instruction is executed.\n \n Radian to Degrees (DEG) Use this instruction to convert radians (source) to degrees and store the result \nin the destination. The \nparticular bit that is turned on depends on the value of the first four bits of the \nsource word. Only the \nfirst four bits (0 to 3) are used by the DCD instruction. The remaining \nbits may be used for other application specific needs. Only one bit of this \nword should be on at any time. If more than one bit in the source is set, \nthe destination bits are set based on the least significant bit that is set. For example, if the destination file type is a counter and the source \nfile type is an integer, three integer words are transferred for each element in \nthe counter-type file.\n \n After a COP or FLL instruction is executed, index register S:24 is cleared to \nzero.\n \n Using COP\n \n This instruction copies blocks of data from one location into another. It uses \nno status bits. If you need an enable bit, program an output instruction (OTE) \nin parallel using an internal bit as the output address. If the destination \n \n file type is 3 words per element (Timer or Counter), you can specify a \nmaximum length of 42. Elements are copied in ascending order.\n \n If your destination file type is a timer, counter, or control file, be sure that the \nsource words corresponding to the status words of your destination file \ncontains zeros.\n \n Be sure that you accurately specify the starting address and length of the data \nblock you are copying.FARANDAWAYCYCLING.COM/images/bosch-maxx-6-sensitive-vaskemaskine-manual.pdf