intel 8086 instruction manual

intel 8086 instruction manual

By using our website and services, you expressly agree to the placement of our performance, functionality and advertising cookies. Please see our Privacy Policy for more information. Update your browser for more security, comfort and the best experience for this site. Try Findchips PRO Additional copies of this manual or, Contents CHAPTER 1 Introduction Manual Organization.PSE Page Size Extension The processor supports, -485 Is it an 8086 processor.Intel Architecture Software Developer's Manual 47-171 I 47.8, executed at the virtual- 8086 mode.In situations, current privilege level is not 0. Real-Address Mode Exceptions None. Virtual- 8086 Mode Exceptions Virtual- 8086,. Provides the programming environment of the Intel 8086 processor with a few extensions (such as the,, a set of general data registers, a set of Intel Architecture Software Developer's Manual,, Protected-Mode Memory Management, of the Intel Architecture Software Developer's Manual, Volume 3. The following. CPU clock rate 5 MHz to 10 MHz Data width 16 bits Address width 20 bits Architecture and classification Min.It was an attempt to draw attention from the less-delayed 16- and 32-bit processors of other manufacturers (such as Motorola, Zilog, and National Semiconductor ) and at the same time to counter the threat from the Zilog Z80 (designed by former Intel employees), which became very successful. Both the architecture and the physical chip were therefore developed rather quickly by a small group of people, and using the same basic microarchitecture elements and physical implementation techniques as employed for the slightly older 8085 (and for which the 8086 also would function as a continuation). The programming model and instruction set is (loosely) based on the 8080 in order to make this possible. However, the 8086 design was expanded to support full 16-bit processing, instead of the fairly limited 16-bit capabilities of the 8080 and 8085. According to principal architect Stephen P.http://www.juliakunovska.sk/userfiles/bridgemaster-radar-technical-manual.xml

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Morse, this was a result of a more software-centric approach than in the design of earlier Intel processors (the designers had experience working with compiler implementations). Other enhancements included microcoded multiply and divide instructions and a bus structure better adapted to future coprocessors (such as 8087 and 8089 ) and multiprocessor systems.The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the Intel 286 and the Intel 386, all of which eventually became known as the x86 family. (Another reference is that the PCI Vendor ID for Intel devices is 8086 h.)The data bus is multiplexed with the address bus in order to fit all of the control lines into a standard 40-pin dual in-line package. Programming over 64 KB memory boundaries involves adjusting the segment registers (see below); this difficulty existed until the 80386 architecture introduced wider (32-bit) registers (the memory management hardware in the 80286 did not help in this regard, as its registers are still only 16 bits wide).The former mode is intended for small single-processor systems, while the latter is for medium or large systems using more than one processor (a kind of multiprocessor mode). Maximum mode is required when using an 8087 or 8089 coprocessor. The workings of these modes are described in terms of timing diagrams in Intel datasheets and manuals. In minimum mode, all control signals are generated by the 8086 itself.Four of them, AX, BX, CX, DX, can also be accessed as twice as many 8-bit registers (see figure) while the other four, SI, DI, BP, SP, are 16-bit only.At most one of the operands can be in memory, but this memory operand can also be the destination, while the other operand, the source, can be either register or immediate.http://www.istambul.com.br/aprovacao/biblioteca/imagens/arquivos/bridgemate-manual.xml

A single memory location can also often be used as both source and destination which, among other factors, further contributes to a code density comparable to (and often better than) most eight-bit machines at the time.However, 8086 registers were more specialized than in most contemporary minicomputers and are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this makes register allocation for compilers more complicated compared to more orthogonal 16-bit and 32-bit processors of the time such as the PDP-11, VAX, 68000, 32016 etc. On the other hand, being more regular than the rather minimalistic but ubiquitous 8-bit microprocessors such as the 6502, 6800, 6809, 8085, MCS-48, 8051, and other contemporary accumulator-based machines, it is significantly easier to construct an efficient code generator for the 8086 architecture.There are 256 interrupts, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the return addresses.Nine of these condition code flags are active, and indicate the current state of the processor: Carry flag (CF), Parity flag (PF), Auxiliary carry flag (AF), Zero flag (ZF), Sign flag (SF), Trap flag (TF), Interrupt flag (IF), Direction flag (DF), and Overflow flag (OF).Near pointers are 16-bit offsets implicitly associated with the program's code or data segment and so can be used only within parts of a program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also support huge pointers, which are like far pointers except that pointer arithmetic on a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointer wraps around within its 16-bit offset without touching the segment part of the address. The tiny model means that code and data are shared in a single segment, just as in most 8-bit based processors, and can be used to build.

com files for instance. Precompiled libraries often come in several versions compiled for different memory models. However, as this would have forced segments to begin on 256-byte boundaries, and 1 MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low cost 40-pin package for the additional four address bus pins.This would mean that all instruction object codes and data would have to be accessed in 16-bit units. Users of the 8080 long ago realized, in hindsight, that the processor makes very efficient use of its memory.The first 8-bit opcode will shift the next 8-bit instruction to an odd byte or a 16-bit instruction to an odd-even byte boundary.If memory addressing is simplified so that memory is only accessed in 16-bit units, memory will be used less efficiently. Intel decided to make the logic more complicated, but memory use more efficient.This allows 8-bit software to be quite easily ported to the 8086.This kind of calling convention supports reentrant and recursive code, and has been used by most ALGOL-like languages since the late 1950s.The 8086 provides dedicated instructions for copying strings of bytes. These instructions assume that the source data is stored at DS:SI, the destination data is stored at ES:DI, and that the number of elements to copy is stored in CX. The above routine requires the source and the destination block to be in the same segment, therefore DS is copied to ES. The loop section of the above can be replaced by:The REPNZ instruction causes the following MOVSB to repeat until CX is zero, automatically incrementing SI and DI and decrementing CX as it repeats. Alternatively the MOVSW instruction can be used to copy 16-bit words (double bytes) at a time (in which case CX counts the number of words copied instead of the number of bytes).

Most assemblers will properly recognize the REPNZ instruction if used as an in-line prefix to the MOVSB instruction, as in REPNZ MOVSB.The copy will therefore continue from where it left off when the interrupt service routine returns control.As instructions vary from one to six bytes, fetch and execution are made concurrent and decoupled into separate units (as it remains in today's x86 processors): The bus interface unit feeds the instruction stream to the execution unit through a 6-byte prefetch queue (a form of loosely coupled pipelining ), speeding up operations on registers and immediates, while memory operations became slower (four years later, this performance problem was fixed with the 80186 and 80286 ). However, the full (instead of partial) 16-bit architecture with a full width ALU meant that 16-bit arithmetic instructions could now be performed with a single ALU cycle (instead of two, via internal carry, as in the 8080 and 8085), speeding up such instructions considerably. Combined with orthogonalizations of operations versus operand types and addressing modes, as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below).The reasons why most memory related instructions were slow were threefold:The 80186 and 80286 both had dedicated address calculation hardware, saving many cycles, and the 80286 also had separate (non-multiplexed) address and data buses.Manufacturers like Cyrix (8087-compatible) and Weitek ( not 8087-compatible) eventually came up with high-performance floating-point coprocessors that competed with the 8087.Such relatively simple and low-power 8086-compatible processors in CMOS are still used in embedded systems. The resulting chip, K1810VM86, was binary and pin-compatible with the 8086.The EC1831 was the first PC-compatible computer with dynamic bus sizing (US Pat.

No 5,548,786) and some other machines (UK Patent Application, Publication No. GB-A-2211325, Published June 28, 1989).The later Olivetti M24SP featured an 8086-2 running at the full maximum 10 MHz. In addition, it makes PCB layout simpler and boards cheaper, as well as demanding fewer (1- or 4-bit wide) DRAM chips. CS1 maint: date format ( link ) CS1 maint: date format ( link ) CS1 maint: date format ( link ) By using this site, you agree to the Terms of Use and Privacy Policy. And by having access to our ebooks online or by storing it on your computer, you have convenient answers with Intel Manual 8086. To get started finding Intel Manual 8086, you are right to find our website which has a comprehensive collection of manuals listed. Our library is the biggest of these that have literally hundreds of thousands of different products represented. I get my most wanted eBook Many thanks If there is a survey it only takes 5 minutes, try any survey which works for you. The Useiis Manual. Numerics Supplement. July 1980 Digitized by the Internet Archive The Numerics Supplement. July 1980. Additional copies of this manual or other Intel literature may be obtained from. Literature Deparimeni. Intel Corporation Santa Clara, CA9505I. The information in this document is subject to change without notice. Intel Corporation makes no warranty of any kind with regard to this material, including, but not limited Intel Corporation Intel Corporation makes no Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, No part of this document may be copied or reproduced in any form or by any means without the prior The following are trademarks of Intel Corporation and may be used only to identify Intel products: Mullibus. Mullimodule Insite. Inlel. Library Manager Micromap. Inieles tsion These processors Microsystem 80 Nomenclature.

Over the last several years, the increase in As Intel's product line has grown and evolved, its In order to accommodate these new VLSI We've adopted the following prefixes to provide Microsystem 80 related product lines: Concentrating on the iAPX Series, two Processor. Families are defined: With additional suffix information, configura- This nomenclature is intended as an addition to This improved nomenclature provides a more The components in the iAPX 86, 88 product lines Using the same family of The iAPX 86, 88 product line architecture is Microprocessors. At the core of the product line are four Multiprocessing. Emplo\ing multiple processors in medium to System Using 8085 Family of Components. The IAPX 86, 88 product line architecture is The architecture supports two types of pro- The lOP starts its channels in response to an The iAPX 86, 88 product line architecture also The coprocessor adds additional register, The iAPX 86, 88 provides built-in solutions to In all cases, the arbitra- For mutual exclusion, each processor has a. LOCK (bus lock) signal which a program may The lOP may lock the This instruction can be Bus Organization. Figure iii summarizes the IAPX 86, 88 bus struc- The iAPX 86, 88 Local Bus. The local bus is optimized for use by the iAPX 86, MCS-85 peripheral components can be directly This allows several Multiple processors connected to the same local Because the System Bus. A full implementation of an iAPX 86, 88 system A group of bus inter- The number of bus inter- The iAPX 86, 88 system bus is functionally and Processing Modules and Bus Topology. The processor(s) and bus interface group(s) that One bus interface If there are multiple pro- A second bus interface group may be connected It can also Table of Contents Evolution S-1. Performance S-3. Usability S-3. Applications S-4. Programming Interface S-5. Hardware Interface S7. Processor Architecture S-7. Control Unit S-8. Numeric Execution Unit S-9. Register Stack S-9. Status Word S-10.

Control Word S-10. Tag Word S-10. Exception Pointers S-11. Computation Fundamentals S-11. Number System S-12. Data Types and Formats S- 1 3. Binary Integers S-14. Decimal Integers S-14. Real Numbers S-15. Special Values S-16. Rounding Control S-17. Precision Control S-17. Infinity Control S-18. Exceptions S-18. Memory S-21. Datastorage S-21. Storage Access S-22. Dynamic Relocation S-22. Dedicated and Reserved Memory Locations... S-22. Multiprocessing Features S-22. Instruction Synchronization S-23. Local Bus Arbitration S-24. System Bus Arbitration S-25. Controlled Variable Access S-25. Processor Control and Monitoring S-26. Initialization S-26. CPU Identification S-26. Interrupt Requests S-27. Interrupt Priority S-27. Endless Wait S-28. Status Lines S-29 Data Transfer Instructions S-30. Arithmetic Instructions S-31. Comparison Instructions S-35. Transcendental Instructions S-36. Constant Instructions S-38. Processor Control Instructions S-39. Instruction Set Reference Information S-42. Execution Time S-44. Bus Transfers S-44. Instruction Length S-44. Programming Facilities S-58 Records and Structures S-60. Addressing Modes S-61 Programming Example S-63. Special Topics S-66. Nonnormal Real Numbers S-67. Denormals S-67. Unnormals S-69. Zeros and Pseudo-zeros S-70. Inifinities S-72. NANs S-73. Data Type Encodings S-74. Exception Handling Details S-75. Programming Examples S-82. Conditional Branching S-82 Tables S-3 Principal Instructions S-6. S-4 Real Number Notation S-15. S-5 Rounding Modes S-17. S-6 Exception and Response Summary S-20. S-7 Processor State Following. S-8 Bus Cycle Status Signals S-28. S-9 Data Transfer Instructions S-30. S-10 Arithmetic Instructions S-32. S-1 1 Basic Arithmetic Instructions S-12 Comparison Instructions S-36. S-13 FXAM Condition Code Settings S-37. S-1 4 Transcendental Instructions S-37. S-15 Constant Instructions S-38. S-16 Processor Control Instructions S-39. S-17 Key to Operand Types S-42. S-18 Execution Penalties S-43.

S-19 Instruction Set Reference Data S-44. S-21 Storage Allocation Directives S-60. S-22 Addressing Mode Examples S-62. S-23 Denormalization Process S-68. S-24 Exceptions Due to Denormal. Operands S-69. S-25 Unnormal Operands and Results S-70. S-26 Zero Operands and Results S-71. S-27 Infinity Operands and Results S-72. S-28 Binary Integer Encodings S-75. S-29 Packed Decimal Encodings S-76. S-30 Real and Long Real Encodings S-76. S-31 Temporary Real Encodings S-77. S-32 Exception Conditions and Masked. Responses S-79. S-33 Masked Overflow Response for. Directed Rounding S-81. A-1. Instruction Encoding A-1. A-2. Machine Instruction Decoding. Guide A-2. Illustrations Diagram S-2. S-2 8087 Evolution and Relative. Performance S-2. S-3 NDP Interconnect S-7. S-4 8087 Block Diagram S-8. S-5 Register Structure S-9. S-6 Status Word Format S-10. S-7 Control Word Format S-11. S-8 Tag Word Format S-12. S-9 Exception Pointers Format S-12. S-10 8087 Number System S-13. S-11 Data Formats S-14. S-12 Projective Versus Affine Closure S-18. S-13 Storage of Integer Data Types S-21. S-14 Storage of Real Data Types S-21. S-15 Synchronizing Execution With S-17 Interrupt Request Path S-29. S-20 Sample 8087 Constants S-43. S-21 Status Word RECORD Definition S-62. S-22 Structure Definition S-62. S-24 Sample ASM-86 Program S-65. S-25 Instructions and Register Stack S-68. S-26 Conditional Branching for Compares S-82. S-27 Conditional Branching for FXAM S-83. S-28 Full State Exception Handler S-86. S-29 Latency Exception Handler S-87. S-30 Reentrant Exception Handler S-87 Data Processor Processor (NDP). Its organization is similar to Manual: Section 1 covers both hardware and software Sections 2 and 4 through NDP that will be of interest to specialized groups Appendix B, as well as in Chapter 4 of The 8086. Family User's Manual. Note that throughout this supplement the term To make best use of S.1 Processor Overview.

The 8087 Numeric Data Processor is a The 8087 is the only chip required to add exten- It is specifically The NDP is The description of the 8087 in this section Subsequent sections of Evolution. The performance of first- and second-generation The 8086 and 8088 CPUs broke the 64k memory Figure S-2 illustrates the progression of Intel In the mid-1970's, Intel Diagram Performance These routines per- FPAL multiply executes in about 1.5 ms (1.6. MHz 8080A CPU). The next product, the iSBC The 8232 accepts It performs a single In 1979, a working committee of the Institute for. Electrical and Electronic Engineers (IEEE) pro- The 8087 Numeric Data Processor is the most Point Anlhmelk,'' ACM SIGNUM Newsletter, October 1979. The NDP also pro- Performance. As figure S-2 indicates, the 8087 provides about Of course, the actual Table S-1 compares the execution times of several NDP development tool discussed later in this The performance figures quoted in this section The 8087's unique coprocessor interface to the. CPU can yield an additional performance incre- Moreover, built-in coordination facilities allow Usability. Viewed strictly from the standpoint of raw speed, By synthesizing advances The 8087 is explicitly designed to deliver stable, While this statement may seem trivial, experi-. Table S-1. 8087 Emulator Speed Comparison. Instruction Multiply (single precision) Straightforward To obtain correct results General application programmers using straight- This simple fact It can process Exact arithmetic is vital in The NDP contains a number of facilities that can Examples of these advanced features include two Applications. The NDP's versatility and performance make it In general, applications Note also that the 8087 can reduce software A few examples, which show how the 8087 might Its built-in The preceding examples are oriented toward. There are, Programming Interface.

The combination of an 8086 or 8088 CPU and an The programming languages and the coprocessor Table S-2 lists the seven 8087 data types. Inter- Moreover, a rounding error does not occur when Computations in the 8087 center on the pro- These eight 80-bit registers This generous Table S-3 lists the 8087's major instructions by Intel's high-level language for the 8086 and 8088 Two features of the 8087 hardware further Data Type. Bits. Significant. Digits (Decimal). Approximate Range (Decimal). Word integer Since the NDP The next instruction is decoded simultaneously by The CPU ex ecutes Since TEST BUSY. The next instruction is interpreted as a This time, in- When the NDP FWAIT to ensure that the 8087 has updated. BETA before it moves BETA'S new value to The 8087 CU can execute most processor control The assembler Local Bus Arbitration. Whenever an NDP instruction writes data to Connecting it to Note that an T he N DP requests the local. If the CPU has The CPU grants the bus NDP can all reside on the same local bus, sharing When th e 8087 detects a bus request pulse on If it is idle CPU so it grants the bus directly at the end of the This satisfies the typical System Bus Arbitration. A single 8288 Bus Controller (plus latches and The 8087 per- CPU; status, address, and data signals and timing In systems that allow multiple processing modules Since only one Because it presents the same system bus interface Controlled Variable Access. If an 8087 and a processor other than its host. CPU can both update a variable, access to that Monitoring. The FINIT (intialize) and FSAVE (save state) RESET pulse, software initialization does not Initialization. The NDP may be initialized by hardware or soft- The state of S-7. Hardware initialization also causes the 8087 Initialization However, since the stack is effectively emptied by CPU Identification.

The 8087's bidirectional BHE (bus high enable) The 8088 always holds Following RESET, the CPU always performs a CPU is an 8086 (because the first fetch is an even- Table S-7, Processor State Following Initialization. Field. Value. Interpretation. Control Word. Infinity Control Rounding Control Precision Control Interrupt-enable Mask Exception Masks Status Word. Busy Condition Code Stack Top Interrupt Request Exception Flags Tag Word. Tags Registers Exception Pointers. Instruction Code Instruction Address Operand Address The 8087 can request an interrupt of its host CPU Controller (PIC). The 8087 should not be tied to All 8087 interrupt requests originate in the detec- The interrupt request logic is The interrupt request If the exception is unmasked but interrupts are If the CPU The 8087 CU con- Normally in this situa- This will clear the If the CPU is waiting, then the processors are in The interrupt request bit remains set until it is This can be done by the. FNCLEX, FNSAVE, or FNINT instructions. The If it does not, the Interrupt Priority. Most systems can be viewed as consisting of two Interrupt handlers execute Since the 8259A typically monitors several events, Application tasks execute only when no external In effect, any inter- There are two important questions to consider Given these considerations, the 8087 should This allows the If an interrupt handler uses the 8087 and requires Then, any un- If, for some reason, the 8087 must be given higher FNDISI instructions before enabling CPU inter- Note No. AP-59, for a description of the 8259A's Endless Wait. The 8087 and its host CPU can enter an endless WAIT instruction and a pending interrupt request Figure S-17 shows the typical path of an interrupt The first block can occur at the 8087's interrupt- A given interrupt request, IRn, can be masked on PlC's interrupt mask register (IMR). This will CPU clears the interrupt path from the 8087.

If, in this condition, the exception handler issues To prevent CPU before executing any instruction that is More generally, an instruction that is preceded by Status Lines. When the 8087 has control of the local bus, it Table S-8, Bus Cycle Status Signals. So. Type of Bus Cycle Status line S7 is currently identical to BHE of the This section describes the operation of each of the The first part of the The second part Throughout this section, the instruction set is Appendix A covers The instruction descriptions in this section con- The typical NDP instruction accepts one or twc. Operands are Still others accept one Whether supplied by the programmer or utilized Even when an instruction converts the source It is distinguished Many instructions allow their operands to be cod- For example, FADD The instruction descriptions in this section Consecutive slashes in- This means that FADD may be written in any of When reading this section, it is important Data Transfer Instructions. These instructions (summarized in table S-9) Any of the seven data types can be converted to The data transfer FLD source. FLD (load real) loads (pushes) the source operand This is done by Short and long real source operands are converted Coding FLD. ST(0) duplicates the stack top. Table S-9. Data Transfer Instructions. Real Transfers. FLD Load real. FST Store real. FSTP Store real and pop. FXCH Exchange registers. Integer Transfers. FILD Integer load. FIST Integer store. FISTP Integer store and pop. Packed Decimal Transfers. FBLD Packed decimal (BCD) load. FBSTP Packed decimal (BCD) store and pop. FST destination. FST (store real) transfers the stack top to the Mnemonics ? Intel1980 If, however, the stack top is tagged special (it con- Neither is the This preserves the Flop Integer compare. Exceptions: 1, D. Operands. Execution Clocks. Transfers. Bytes. Coding Example. Typical. Range Integer compare and pop. Range Operands. Range Integer divide reversed. Exceptions: 1, D, Z, 0, U, P.

Range Integer load. Exception: 1. Range Integer multiply. Exceptions: 1, D, 0, P. Range Increment stack pointer. Exceptions: None. Range Initialize processor. Range Integer store. Range Integer store and pop. Range FSTENV and FLDENV instructions. Addressing Modes CPU's five memory addressing modes. This Table S-22 gives several examples of 8087 instruc- Intel offers two software products that provide The partial emulator (PE8087) is a smaller version The emulators may be viewed as consisting of The emulators establish in CPU memory the The emulator Emulator instructions are Coding. Interpretation Since the decision to produce real or emulated This reference is satisfied by linking the object If the real To run on an emulated 8087, the object program Note that an explicitly-coded CPU WAIT instruc- This is why In order to be compatible with E8087, ASM-86 FINIT instruction. If the program is not FINIT instruction. ASM-86 code for a simple 8087 program, called. ARRSUM. The program references an array Either version of the program will run on an SUMSINDEXES, the built-in procedure FLOAT The ASM-86 version (figure S-24) defines the After defining the data, and setting up the seg- As shown in figure. S-25, these registers remain at the bottom of the The program uses the CPU LOOP instruction to CX, which LOOP automatically decrements, is Register SI is used to The program ASM-86 TYPE operator is used to determine the Figure S-25 shows the effect of the instructions in This section describes features of the 8087 which Most users will not need to Most readers, then, At the end of the section Mnemonics 1 Intel 1978. 1980 Nonnormal Real Numbers. As discussed in section S.3, the 8087 generally Denormals. A denormal is the result of the NDP's masked For example, a true exponent of -130 will cause The constant The intent of the masked response to underflow is Roundoff (preci- Recognizing The 8087's masked Table S-23 Denormalization produces a denormal or a zero.

Denormals are readily identified by their The denormalization process may cause the loss In this case, the result of However, this is Denormals are rarely encountered in most Table S-23. Denormalization Process. Operation. Sign. Significand. True Result Denormals are If storage Accessing a denormal may produce an exception Denormals may have reduced significance due to IEEE standard precludes operations on non- As table S-24 shows, the division and remainder Recall, also, Unnormals An unnormal may exist only in the temporary real Unnormals allow arithmetic to continue follow- That is, unnormal operands generate unnormal Unnormals are thus Table S-25 shows how the instruction set deals Note that the unnormal Table S-24. Exceptions Due to Denormal Operands. Exception. Masked Response Compare and test Division or FPREM with Operation. Result Short. Long. If this encoding is used as a source operand The 8087 will deliver Table S-32 lists every exception condition that the. NDP detects and describes the processor's The unmasked responses are described in table. S-6. Note that if an unmasked overflow or When rounding is directed (the RC field of the In all masked overflow responses for directed Class. Magnitude Positives Zero Class. Biased. Exponent. Aff.ff. Zero Table S-3 1. Temporary Real Encodings. Class. Significand Positives. NANs Class. Significand Zero Class. Biased Significand Negatives Condition. Masked Response. Invalid Operation. Source register is tagged empty (usually Return real indefinite. Destination register is not tagged empty Return real indefinite (overwrite One or both operands is a NAN. Return NAN with larger absolute value Return real indefinite Store mteger indefinite. Store packed decimal indefinite.http://energysatrap.com/images/broan-qs230ss-manual.pdf